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74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs
October 2001 Revised May 2005
74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The 74ALVC16374 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V - 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD
3.5 ns max for 3.0V to 3.6V VCC 4.4 ns max for 2.3V to 2.7V VCC 7.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance:
Human body model ! 2000V Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC16374GX (Note 2) 74ALVC16374MTD (Note 3) Package Number BGA54A MTD48 Package Descriptions 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
(c) 2005 Fairchild Semiconductor Corporation
DS500692
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74ALVC16374
Logic Symbol
Pin Descriptions
Pin Names OEn CPn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Clock Pulse Input Inputs Outputs No Connect
Connection Diagrams
Pin Assignment for TSSOP
NC
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 CP1 NC VCC GND GND GND VCC NC CP2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs CP1 Outputs I0-I7 H L X X O0-O7 H L O0 Z Outputs I8-I15 H L X X O8-O15 H L O0 Z OE1 L L L H Inputs CP2

L X
Pin Assignment for FBGA

L X
OE2 L L L H
H L X Z O0
HIGH Voltage Level LOW Voltage Level Immaterial (HIGH or LOW, inputs may not float) High Impedance Previous O0 before HIGH-to-LOW of CP
(Top Thru View)
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74ALVC16374
Functional Description
The 74ALVC16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC16374
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 5) DC Input Diode Current (IIK) VI 0V DC Output Diode Current (IOK) VO 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (I CC or GND) Storage Temperature Range (TSTG)
0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA r50 mA r100 mA 65qC to 150qC
Recommended Operating Conditions (Note 6)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
40qC to 85qC
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH IOH IOH IOH Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 VCC - 0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 V V V V Max Units
100 PA 4 mA 6 mA 12 mA
1.65 - 3.6 1.65 2.3 2.3 2.7 3.0
IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input
24 mA
100 PA 4 mA 6 mA 12mA 24 mA
3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3 3.6 3.6 0 3.6 3 -3.6
0 d VI d 3.6V 0 d VO d 3.6V VI VIH VCC or GND, IO VCC 0.6V
r5.0 r10
40 750
PA PA PA PA
'ICC
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74ALVC16374
AC Electrical Characteristics
TA Symbol Parameter V CC Min fMAX tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tW tS tH Maximum Clock Frequency Propagation Delay Bus to Bus Output Enable Time Output Disable Time Pulse Width Setup Time Hold Time 250 1.3 1.3 1.3 1.5 1.5 1.0 3.5 4.0 4.0 CL 3.3V r 0.3V Max 50 pF V CC Min 200 1.5 1.5 1.5 1.5 1.5 1.0 4.4 5.1 4.3 2.7V Max V CC Min 200 1.0 1.0 1.0 1.5 1.5 1.0 3.9 4.6 3.8
40qC to 85qC, RL
500: CL 2.5V r 0.2V Max 30 pF V CC Min 100 1.5 1.5 1.5 4.0 2.5 1.0 7.8 9.2 6.8 1.8V r 0.15V Max ns ns ns ns ns ns ns Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VI VI Outputs Enabled f 0V or VCC 0V or VCC 10 MHz, CL 50 pF Conditions TA VCC 3.3 3.3 3.3 2.5
25qC
Typical 6 7 20 20
Units pF pF pF
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74ALVC16374
AC Loading and Waveforms
TABLE 1. TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Symbol Vmi Vmo VX VY VL VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOL 0.3V V6 2.7V 1.5V 1.5V VOL 0.3V VOL 0.3V 6V 2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOL 0.15V VCC*2 1.8V r 0.15V VCC/2 VCC/2 VOL 0.15V VOL 0.15V VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
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74ALVC16374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
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74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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